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p reliminary w78e 858 8 - bit microcontrolle r publication release date: october 9, 2001 - 1 - revision a1 1. general descripti on the w78e858 is an 8 - bit microcontroller which has an in - system programmable flash eprom for firmware updating. the instruction set of the w78e858 is fully compatible with the standard 8052. the w78e858 contains a 32 k bytes of main fl ash eprom and a 4k bytes of auxiliary flash eprom which allows the contents of the 64kb main flash eprom to be updated by the loader program located at the 4kb auxiliary flash eprom rom; 768 bytes of on - chip ram; 128 bytes of eeprom, 8 extra power down wak e - up through int2 to int9 ; 4 channel 8 - bit pwm ; four 8 - bit bi - directional and bit - addressable i/o ports; an additional 4 - bit port p4; three 16 - bit timer/counters where the timer2 with programmable clock output and 17 - bit watchdog timer are built in this de vice; a serial port. these peripherals are supported by a eight sources two - level interrupt capability. to facilitate programming and verification, the flash eprom inside the w78e858 allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. 2. features fully static design 8 - bit cmos micro - controller up to 40 mhz 32k bytes of in - system programmable flash eprom for application program (aprom) 4k bytes of auxiliary flash ep rom for loader program (ldrom) low standby current at full supply voltage 256 + 512 bytes of on - chip ram 128 bytes on - chip eeprom memory 64k bytes program memory address space and 64k bytes data memory address space four 8 - bit bi - directional port s one 4 - bit bi - directional port extra interrupts int2 to int9 at port1 wake - up via external interrupts int0 - int9 three 16 - bit timer/counters one full duplex serial port fourteen - sources, two - level interrupt capability programmable timer2 clock output via p1.0 17 - bits watchdog timer four channels 8 - bit pwm built - in power management code protection packaged in pdip 40 / plcc 44 / p qfp 44
p reliminary w78e 858 - 2 - 3. p in configurations 44-pin plcc 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p4.1 p4.3 p 4 . 0 p 1 . 4 p 1 . 3 p 1 . 2 t 2 e x . p 1 . 1 t 2 . p 1 . 0 p 4 . 2 v d d a d 0 . p 0 . 0 a d 1 . p 0 . 1 a d 2 . p 0 . 2 a d 3 . p 0 . 3 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal2 xtal1 vss vcc p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p2.4, a12 p2.3, a11 p2.2, a10 p2.1, a9 p2.0, a8 40-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 34 40 39 38 37 36 33 32 31 30 29 28 27 26 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea p4.1 ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 p4.3 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 p 1 . 4 p 1 . 3 p 1 . 2 t 2 e x . p 1 . 1 t 2 . p 1 . 0 v d d a d 0 . p 0 . 0 a d 1 . p 0 . 1 a d 2 . p 0 . 2 a d 3 . p 0 . 3 p 4 . 2 44 43 42 41 12 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p 4 . 0 35 25 24 44-pin pqfp
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 3 - revision a1 4. pin description symbol type descr iptions ea i external access enable: ea low forces the processor to execute the external rom. the rom address and data will not be present on the bus if the ea pin is high and the program cou nter is within the 32 kb area. otherwise they will be present on the bus. psen o/h program strobe enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o/h address latch enable: ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. an ale pulse is omitted during external data memory accesses. rst i/l reset: a high on this pin for two machine cycles while the oscillator is running resets the device. rst has a schmitt trigger input stage to provide additional noise immunity with a slow rising input voltage. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock xtal2 o crystal 2: this is the crystal oscillator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power suppl y: supply voltage for operation. p0.0 - p0.7 i/o d port 0: function is the same as that of the standard 8052. p1.0 - p1.7 i/o h port 1: function is the same as that of the standard 8052. port1 also service the alternative function int2 - int9. p1.0 pr ovide a timer2 programmable clock output. four channel pwm clock output via p1.4 - p1.7 p2.0 - p2.7 i/o h port 2: port 2 is a bi - directional i/o port with internal pull - ups and emits the high - order address byte during accesses external memory p3.0 - p3 .7 i/o h port 3: function is the same as that of the standard 8052 p4.0 - p4. 3 i/o h port 4: function is the same as port1 * note: type i: input, o: output, i/o: bi - directional, h: pull - high, l: pull - low, d: open drain
p reliminary w78e 858 - 4 - 5. block diagram ram 256 ram 256 auxiliary ram 512 bytes bytes auxiliary mtp-rom 4k bytes main mtp-rom 32k bytes cpu core sfr port0 port1 port2 port4 timer2 pwm timer1 int0 int1 int2~9 watch-dog uart timer0 port3 power down wake up eeprom 128 bytes programmable clock output interrupts 8051 data bus 6. functional descri ption the w78e858 architecture consists of a core controller surrounded by various registers, four 8 - bit general purpose i/o ports, one 4 - bits general purpose i/o port, 256 bytes data ram and 512 bytes auxiliary ram, 128 b ytes embedded eeprom memory, three timer/counters, one serial port, 17 - bit watch - dog timer, 8 - bit four channels pwm, programmable timer2 clock output, extra external interrupts int2 to int9, power - down wake up via external interrupts int0 - int9. and a bla ck box of eastern pay tv control block. the cpu supports 111 different op - codes and references both a 64k program address space and a 64 k data storage space. ram the internal data ram in w78e858 is 768 bytes. it is divided into two banks: 256 bytes of dat a ram and 512 bytes of auxiliary ram. these ram are addressed by different ways. ram 00h - 7fh can be addressed directly and indirectly as the same as in 80c51. address pointers are r0 and r1 of the selected register bank. ram 80h - ffh can only be address ed indirectly as the same as in 80c51. address pointers are r0, r1 of the selected registers bank. auxiliary ram 0000h - 01ffh is addressed indirectly as the same way to access external data memory with the movx instruction. address pointers are r0 and r1 of the selected register bank and dptr register. by setting enauxram flag in chpcon register bit4 to enable on - chip auxiliary ram 512 bytes. when the auxiliary ram is enabled, the data and address will not appear on p0 and p2, they will keep their previous status that before the movx instruction be executed. write the page select 00h or 01h to mxpsr register if r0 and r1 are used as address pointer. when the address of external data memory locations higher than 01ffh or disable auxiliary ram 512 bytes micro - controller will be performed with the movx instruction in the same way as in the 80c51. the auxiliary ram 512 bytes default is disabled after chip reset.
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 5 - revision a1 eeprom the 128 bytes eeprom is defined in external data memory space that located in ff80h - ffffh in s tandard 8 - bit series. it is accessed the same as auxiliary ram512 bytes, the eneeprom flag in chpcon register bit5 is set. write the page select 03h to mxpsr register, r0 and r1are used as address pointer. the eeprom provided byte write, page write mode an d software write protection is used to protect the data lose when power on or noise. they are described as below: byte write mode once a byte write has been started, it will automatically time itself to completion. a busy signal will be used to detect the end of write operation. page write mode the eeprom is divided into 2 pages and each page contains 64 bytes. the page write allows one to 64 bytes of data to be written into the memory during a single internal programming cycle. page write is initiated in t he same manner as byte write mode. after the first byte is written, it can then be followed by one to 63 additional bytes. if a second byte is written within a byte - load cycle time (tblc) of 150us, the eeprom will stay at page load cycle. additional bytes can then be loaded consecutively. the page load cycle will be terminated and the internal programming cycle will start if no additional byte is load within 300us from the last byte be loaded. the address bit6 specify the page address. all bytes that are lo aded to the buffer must have the same page address. the data for page write may be loaded in any order, the sequential loading is not required. software protected data write the eeprom provides a jeded - approved optional software - protected data write. onc e this scheme is enabled, any write operation requires a series of three - byte program commands (with specific data to a specific address) to be performed before the data load operation. the three - byte load command sequence begins the page load cycle, witho ut which the write operation will not activated. this write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power - up or power - down. once enabled, the software data protection will remain enabled unless the disable commands are issued. to reset the device to unprotected mode, a six - byte command sequence is required. the address mapping of the external memory is given as following, if enauxram or eneeprom flags in chpcon is not set, the cpu will access external memory instead of the on - chip memory. the data, address and read/write strobe signal will appear on relative io port just like standard 80c52. command codes for software data protection enable/disable and software erase byte enable wr ite protect disable write protec t software erase sequence address data address data address data 0 write ff55h aah ff55h aah ff55h aah 1 write ff2ah 55h ff2ah 55h ff2ah 55h 2 write ff55h a0h ff55h 80h ff55h 80h 3 write - - ff55h aah ff55h aah 4 write - - ff2ah 55h ff2ah 55h 5 write - - ff55h 20h ff55h 10h note: for eastern pay tv application, the high order address byte is 02h.
p reliminary w78e 858 - 6 - auiliary ram 512 bytes 0000h 01ffh 0200h eeprom 128 bytes ff80h ffffh external memory fig. on-chip external memory addressed mapping (a) standard 51 series software data protection enable flow load data aah to address ff55h load data 55h to address ff2ah load data a0h to address ff55h load data aah to address ff55h load data 55h to address ff2ah load data 80h to address ff55h load data aah to address ff55h load data 55h to address ff2ah load data 20h to address ff55h software data protection disable flow load data aah to address ff55h load data 55h to address ff2ah load data 80h to address ff55h load data aah to address ff55h load data 55h to address ff2ah load data 10h to address ff55h software erase flow software data protection and erase acquisition flow
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 7 - revision a1 on - chip flash eprom the w78e858 includes two banks of flash eprom. one is 32k bytes of main flash eprom for application program (aprom) and another 4k bytes of flash eprom for loader program (ldrom) when operating the in - system programming feature. in normal operation, the micro - controller will execute the code fro m the 32k bytes of aprom. by setting program registers, user can force cpu to switch to the programming mode which will execute the code (loader program) from the 4k bytes of auxiliary ldrom, and this loader program is going to update the contents of the 3 2k bytes of aprom. after chip reset, the micro - controller executes the new application program in the aprom. this in - system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. in some applicati ons, the in - system programming feature make it possible that end - user is able to easily update the system firmware by themselves without opening the chassis. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8 - bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture r egisters for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a 16 - bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event count er or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto - reload, and baud rate generator. the clock speed at capture or auto - reload mode is the same as that of timers 0 and 1. clock the w78 e858 is designed to use with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used by default. this makes the w78e858 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78e858 incorporates a built - in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from x tal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos - type input, as required by the crystal oscilla tor. as a result, the external clock signal should have an input one level of greater than 3.5 volts. power management idle mode the cpu will enter to idle by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor i s stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs.
p reliminary w78e 858 - 8 - power - down mode when the pd bit of the pcon register is set, the processor enters the power - down mode. in this mode all of the clocks, including the oscillator are stopped. there are two ways to exit power - down mode, one is by a chip reset and another is via external interrupts wake up if the related control flags are enabled. wake - up via external interrup ts int0 to int9 if the external interrupts int0 to int9 are enabled, the w78e858 can be awakened from power down mode with the external interrupts if the ea flag in ie register and related interrupt enable is set before enter power down mode. to ensure tha t the oscillator is stable before the controller starts, the internal clock will remain inactive for some oscillator periods. this is controlled by a on - chip delay counter. the delay time is software selectable and the reset default value is 1536 periods. by setting the ps2 - ps0 bits in auxr register the delay periods is given as below: ps2 ps1 ps0 delay periods delay time (20 mhz) 0 0 0 192 0.0096 ms 0 0 1 384 0.0192 ms 0 1 0 768 0.0384 ms 0 1 1 1536 0.0768 ms 1 0 0 3072 0.1536 ms 1 0 1 6144 0.372 m s 1 1 0 12288 0.6144 ms 1 1 1 24576 1.2288 ms interrupt in0~int9 oscillator reset-pin power-down delay counter x tosc > 24 x tosc .... ... internal clock fig. power-down wake up operation
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 9 - revision a1 or8 wake up p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ix1 ien1 irq1 x9 x2 x3 x4 x5 x6 x7 x8 fig. port1 external interrupt configuration reset the external rst signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to deglitch the reset line when the ra80xx is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. w78e858 special function registers and reset values f8 +ip1 0000000 ff f0 +b 00000000 chpenr 00000000 f7 e8 +ie1 00000000 ix1 00000000 ef e0 +acc 00000000 e7
p reliminary w78e 858 - 10 - w78e858 special function registers and reset values, continued d8 +p4 11111111 df d0 +psw 00000000 d7 c8 +t2con 00000000 t2mod xxxxxx0x rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 +irq1 00000000 sfral 00000000 sfrah 00000000 sfrfd 00000000 sfrcn 00000000 c7 b8 +ip 000000 chpcon 0xx00000 bf b0 +p3 00000000 b7 a8 +ie 01000000 af a0 + p2 11111111 mxpsr 0xxxx000 a7 98 +scon 00000000 sbuf xxxxxxxx 9f 90 +p1 11111111 pwmcn xxxx0000 pwmp 00000000 dac0 00000000 dac1 00000000 dac2 00000000 dac3 00000000 97 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 auxr xxxx0110 wdtc 000xx000 8f 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 wdtest -------- pcon 00110000 87 note: the sfrs marked with a plus sign(+) are both byte and bit - addressable. pulse width modulator system the pulse width modulator system of w78e858 contains four pwm output channels with a common 8 - bit counter. these channels generate pulses of programmable length and interval. the prescaler and counter are common to four pwm channels. pwcon (c3h) bit name function 7 - 4 - reverse 3 pwm3 enable p1.7 as pwm clock output. 2 pwm2 enable p1.6 as pwm clock output. 1 pwm1 enable p1.5 as pwm clock output. 0 pwm0 enable p1.4 as pwm clock output. pwmp (92h) the prescaler is loaded with the complement of the pwmp register during counter overflow. the repetition frequency is defined by 8 - bit prescaler which clocks the counter. the prescaler division factor = (pwmp + 1). reading the pwmp gives the current reload value. the actual count of the prescaler can?t be read.
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 11 - revision a1 the pwm counter is enabled with any bit pwen (n = 0, 1, 2, 3) of the pwcon register. output to the port pin is separately enabled by setting the pwen bits in the pwcon register. the pwm function is reset by a chip reset. in idle mode, the pwm will function as con figurated in pwcon. in power - down state of the pwm will freeze when the internal clock stops. if the chip is awakened with an external interrupt, the pwm will continue to function its state when power - down was entered. the repetition frequency is given by: fpwm = fosc [255 x (1+pwmp)] an oscillator frequency of 24 mhz results in a repetition range of 367.65 hz to 94.12 khz. the high/low ratio of pwmn is dacn/(255 - dacn) for dacn values except 255. a dacn value 255 results in a high pwmn output. pwmen0 pwmen1 pwmen2 pwmen3 endac or pwmp sfr 8-bit prescaler 8-bit up counter dac2 8-bit detect 8-bit detect dac3 dac0 8-bit detect 8-bit detect dac1 and fosc internal bus output buffer output buffer output buffer output buffer p1.4 p1.5 p1.6 p1.7 fig. four channels 8-bit pwm function block diagram in - system programming system the w78e858 provided in - system programming function for new firmware updated. after the related register and flags are set, user can start timer and force the cpu enter idle mode, then w78e858 will perform the in - system pr ogram mode function specify in sfrcn register, the destination data and address will come from the related sfr.
p reliminary w78e 858 - 12 - the chpcon is read only by default. firmware designer must write 87h, 59h sequentially to this special register chpenr to enable the chpcon wri te attribute, and write other value to disable chpcon write attribute. this register protects from writing to the chpcon register carelessly. sfral (c4h) the programming low - order byte address of flash eprom in - system programming mode sfrah (c5h) the prog ramming high - order byte address of flash eprom in - system programming mode sfrfd (c6h) the programming data for on - chip flash eprom in - system programming mode sfrcn (c7h) bit name function 7 - reserve. 6 wfwin on - chip flash eprom bank select for in - syst em programming. = 0: 32 k bytes flash eprom bank is selected as destination for re - programming. = 1: 4k bytes flash eprom bank is selected as destination for re - programming. 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3 - 0 ct rl[3:0] the flash control signals in - system programming mode operating table mode ctrl<3:0> wfwin oen cen sfral sfrah sfrfd erase 32k aprom 0010 0 1 0 x x x erase 4k ldrom 0010 1 1 0 x x x program 32k aprom 0001 0 1 0 address address data in progra m 4k ldrom 0001 1 1 0 address address data in read 32k aprom 0000 0 0 0 address address data out read 4k ldrom 0000 1 0 0 address address data out
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 13 - revision a1 chpcon (bfh) bit name function 7 swreset (f04kmode) when this bit is set to 1, and both fbootsl and fpr ogen are set to 1. it will enforce microcontroller reset to initial condition just like power on reset. this action will re - boot the microcontroller and start to normal operation. to read this bit can determine that the f04kboot mode is running. 6 - re serve. 5 eneeprom enable on - chip 128 bytes eeprom. 4 enauxram enable on - chip 512 bytes auxiliary ram. 3 - 2 - - 1 fbootsl the loader program location selection. = 0: loader program in 32k memory bank. = 1: loader program in 4k memory bank. 0 fprogen i n system programming enable flag. = 1: enable. the cpu switches to the programming flash mode after entering the idle mode and waken up from interrupt. the cpu will execute the loader program while in on - chip programming mode. = 0: disable. the on - chip fla sh eprom read - only. in - system programmability is inhibit. interrupt system external events and the real - time - driven on - chip peripherals require service by the cpu asynchronous to do execution of any particular section of code. to tie the asynchronous acti ves of these functions to normal program execution, a multiple - source, two - priority - level, nested interrupt system is provided. the w78e858 acknowledges interrupt requests from fourteen sources as below: int0 and int1 timer0 and timer1 uart serial i/o int2 to int9 (at port1) external interrupts int2 to int9 port1 lines serve an alternative purpose at eight additional interrupts int2 to int9. when enabled, each of these lines may " wake - up " the device from power - down mode. using the ix1 register, the each pin may be initialized to either active high or low. irq1 is the interrupt request flag register. each flag, if the interrupt is enabled will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disable. the port1 interrupts are level sensitive. a port1 interrupt will be recognized when a level (high or low depending on interrupt polarity register ix1) on p1.x is held active for at least one machine cycle. the interrupt request is not served u ntil the next machine cycle.
p reliminary w78e 858 - 14 - ie1 (e8h) bit name function 7 ex9 enable external interrupt 9 6 ex8 enable external interrupt 8 5 ex7 enable external interrupt 7 4 ex6 enable external interrupt 6 3 ex5 enable external interrupt 5 2 ex4 enable ex ternal interrupt 4 1 ex3 enable external interrupt 3 0 ex2 enable external interrupt 2 ip1 (f8h) bit name function 7 px9 external interrupt 9 priority level 6 px8 external interrupt 8 priority level 5 px7 external interrupt 7 priority level 4 p x6 external interrupt 6 priority level 3 px5 external interrupt 5 priority level 2 px4 external interrupt 4 priority level 1 px3 external interrupt 3 priority level 0 px2 external interrupt 2 priority level ix1 (e9h) bit name function 7 il9 ex ternal interrupt 9 polarity level 6 il8 external interrupt 8 polarity level 5 il7 external interrupt 7 polarity level 4 il6 external interrupt 6 polarity level 3 il5 external interrupt 5 polarity level 2 il4 external interrupt 4 polarity level 1 il3 external interrupt 3 polarity level 0 il2 external interrupt 2 polarity level
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 15 - revision a1 irq1 (c0h) bit name function 7 iq9 external interrupt 9 request flag 6 iq8 external interrupt 8 request flag 5 iq7 external interrupt 7 request flag 4 iq6 exte rnal interrupt 6 request flag 3 iq5 external interrupt 5 request flag 2 iq4 external interrupt 4 request flag 1 iq3 external interrupt 3 request flag 0 iq2 external interrupt 2 request flag interrupt priority and vector address priority interrupt vector source priority interrupt vector source 1 int0 0003h external 0 8 tf1 001bh timer 1 2 int5 0053h external 5 9 sint 0023h uart 3 tf0 000bh timer 0 10 tf2 0033h timer 2 4 int6 005bh external 6 11 int3 0043h external 3 5 int1 0013h external 1 1 2 int8 006bh external 8 6 int2 003bh external 2 13 int4 004bh external 4 7 int7 0063h external 7 14 int9 0073h external 9 f04kboot mode (boot from 4k bytes ldrom) the w78e858 boots from aprom program (32k bytes bank) by default after chip reset. on some occasions, user can force the w78e858 to boot from the ldrom program (4k bank) after chip reset. the setting for this special mode is as follow. f04kboot mode p4.3 p2.7 p2.6 mode x l l fo4kboot l x x fo4kboot note: in application system design, user must take care the p2, p3, ale, ea and psen pin status at reset to avoid w78e858 entering the programming mode or f04kboot mode in normal operation.
p reliminary w78e 858 - 16 - enter 4k reboot mode timing ts=1us th > 24 clocks p2.6 p2.7 x x reset security during the on - chip flash epr om programming mode, the flash eprom can be programmed and verified repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and those operations on it are described below: the w78e858 has several special setting registers in flash eprom block . those bits of the security register can?t be changed once they have been programmed from high to low. they can only be reset through erase - all operation. the security register is located at the ffffh on the same bank with 4k ldrom i.e., p3.6 must set high at writer mode. security register 4kb ldrom ffffh 0000h 0ffeh on-chip reversed lock bit (bit0) this bit is used to protect the customer's program code in the w78e858. it may be set after the programmer finishes the programming and ve rifies sequence. once these bits are set to logic 0, both the flash eprom data and all data in flash eprom block can?t be accessed again. movc lock (bit1) when this bit is program to " 0 " , the movc instruction will be disable when the program counter more than 7fffh or ea pin is forced low.
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 17 - revision a1 scramble enable (bit2) this bit is used to protect the customer's program code in the w78e858. if this bit is set to logic 0, the dump rom code are scrambled by a scramble circuit and the dump rom co de will become a random rom code. oscillator gain select (bit7) if this bit is set to logic 0 (for 24 mhz), the emi effect will be reduce. if this bit is set to logic 1 (for 40 mhz), the w78e858 could to use 40 mhz crystal, but the emi effect is major. so we provide the option bit which could be chose by customer. watch dog timer for more system reliability, w78e858 provides a programmable watch - dog time - out reset function. from programming prescaler select, user can choose a variable prescaler from divide d by 2 to divided by 256 to get a suitable time - out period. the time - out period is given by: t time-out = 1 fosc x 2 14 x prescaler x 1000 x 12 (ms) (note: fosc unit = hz) wdtc (8fh) bit name function 7 enw enable watch - dog timer if set. 6 clrw clear watch - dog timer and prescale r if set. this flag will be cleared auto - matically. 5 widl if this bit is set, watch - dog is enabled under idle mode. if cleared, watch - dog is disable under idle mode. default is cleared. 4 - 3 - reversed. 2 ps2 watch - dog prescaler timer select. 1 ps1 w atch - dog prescaler timer select. 0 ps0 watch - dog prescaler timer select. ps2 ps1 ps0 prescaler selcet watch - dog time - out p eriod (f osc = 20 mhz) 0 0 0 2 19.66 ms 0 0 1 4 39.32 ms 0 1 0 8 78.64 ms 0 1 1 16 157.28 ms 1 0 0 32 314.57 ms 1 0 1 64 629.1 4 ms 1 1 0 128 1.25 ms 1 1 1 256 2.52 ms
p reliminary w78e 858 - 18 - programmable clock - out a 50% duty cycle clock can be programmed to come out on p1.0. to configure the timer/counter2 as a clock generator, bit c/t2 in t2con register must be cleared and bit t2oe in t2mod register must be set. bit tr2 (t2con.2) also must be set to start timer. the clock - out frequency depends on the oscillator frequency and reload value of timer2 capture register (rcap2h, rcap2l) as shown in this equation: )) 2 , 2 ( 65536 ( 4 l rcap h rcap frequency r oscillatot - in the clock - out mo de, timer2 roll - overs will not generate an interrupt. this is similar to when it is used as a baud - rate generator. it is possible to use timer2 as a baud - rate generator and a clock and a clock generator simultaneously. reduce emi emission the transition of ale will cause noise, so it cab be turned off to reduce the emi emission if it is useless. turn off the ale signal transition only need too set the aleoff flag in the auxr register when ale is turned off, it will be reactived when program access external rom or ram data or jump to execute external rom code. after access completely or program returns to internal rom code, ale signal will turn off again. prescaler 14-bit timer external reset system reset enw widl idle fosc 1/12 clrw fig. 17-bit watch-dog timer function block diagram 7. absolute maximum ratings parameter symbol min. max. unit dc power supp ly v dd - v ss - 0.3 +6.0 v input voltage v in v ss - 0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st - 55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and relia bility of the device.
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 19 - revision a1 8. d.c. electrical characteristics (v dd - v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) parameter sym. specification test conditions min. max. unit operating voltage v dd 4.5 5.5 v rst = 1, p0 = v dd operating current i dd - 20 ma no load v dd = 5.5v idle current i idle - 6 ma idle mode v dd = 5.5v power down current i pwdn - 50 m a power - down mode v dd = 5.5v input current p1, p2, p3, p4 i in1 - 50 +10 m a v dd = 5.5v v in = 0v or v dd input current rst i in2 - 10 +300 m a v dd = 5.5v 0 < v in < v dd input leakage current p0, ea i lk - 10 +10 m a v dd = 5.5v 0 < v in < v dd logic 1 to 0 transition current p1, p2, p3, p4 i tl [*4] - 500 - m a v dd = 5.5v v in = 2.0v input low voltage p0, p1, p2, p3, p4, ea v il1 0 0.8 v v dd = 4.5v input low voltage rst v il2 0 0.8 v v dd = 4.5v input low voltage xtal1 [*4] v il3 0 0.8 v v dd = 4.5v input high voltage p0, p1, p2, p3, p4, ea v ih1 2.4 v dd +0.2 v v dd = 5.5v input hig h voltage rst v ih2 3.5 v dd +0.2 v v dd = 5.5v input high voltage xtal1 [*4] v ih3 3.5 v dd +0.2 v v dd = 5.5v output low voltage p1, p2, p3, p4 v ol1 - 0.45 v v dd = 4.5v i ol = +2 ma output low voltage p0, ale, psen [*3] v ol2 - 0.45 v v dd = 4.5v i ol = +4 ma
p reliminary w78e 858 - 20 - d.c. electrical characteristics, continued parameter sym. specification test conditions min. max. unit sink current p1, p3, p4 i sk1 4 12 ma v dd = 4.5v v in = 0.45v sink current p0, p2, ale, psen i sk2 10 20 ma v dd = 4.5v v in = 0.45v output high voltage p1, p2, p3, p4 v oh1 2.4 - v v dd = 4.5v i oh = - 100 m a output high voltage p0, ale, psen [*3] v oh2 2.4 - v v dd = 4.5v i oh = - 400 m a source current p1, p2, p3, p4 i sr1 - 120 - 250 m a v dd = 4.5v v in = 2.4v (latch) source current p0, p2, ale, psen i sr2 - 8 - 20 ma v dd = 4.5v v in = 2.4v notes: *1. rst pin is a schmitt trigger input. *3. p0, ale and psen are tested in the external access mode. *4. xtal1 is a cmos inpu t. *5. pins of p1, p2, p3, p4 can source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in approximates to 2v. 9. ac characteristic s the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will u sually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.6 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 21 - revision a1 parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in oth er specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - d - - ns 4 address hold from ale low t aah 1 t cp - d - - ns 1, 4 ale low to psen low t apl 1 t cp - d - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - d 2 t cp - ns 4 psen pulse width t psw 3 t cp - d 3 t cp - ns 4 notes: 1. p0.0 - p0.7, p2.0 - p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " d " (due to buffer driving delay and wire loading) is 20 ns. data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - d - 3 t cp+ d ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - d 6 t cp - ns 2 notes: 1. data memory access t ime is 8 t cp . 2. " d " (due to buffer driving delay and wire loading) is 20 ns.
p reliminary w78e 858 - 22 - data write cycle parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - d - 3 t cp + d ns data valid to wr low t dad 1 t cp - d - - ns data hold from wr high t dwd 1 t cp - d - - ns wr pulse width t dwr 6 t cp - d 6 t cp - ns note: " d " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port inpu t setup to ale low t pds 1 t cp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t cp - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, sinc e it provides a convenient reference. flash mode timing parameter symbol min. typ. max. unit notes reset valid t rv 9 10 11 m s - enter flash mode reset low t efrl 9 10 11 m s - program pulse high t pph 18 20 22 m s - program pulse low t ppl 135 150 165 m s - erase pulse low t epl 13.5 15 16.5 ms - read pulse low t rpl 1.35 1.5 1.65 m s - address prefix t apf 45 50 55 ns - data remain t dr 81 90 99 ns -
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 23 - revision a1 10. timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar
p reliminary w78e 858 - 24 - timing waveforms, continued data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 25 - revision a1 11. typical applicat ion circuits expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 2764 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 35 xtal1 21 xtal2 22 rst 10 int0 14 int1 15 t0 16 t1 17 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 18 psen 32 ale 33 txd 13 rxd 11 w78e858 10 u 8.2 k dd crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 v dd v figure a crystal c1 c2 r 6 mhz 68p - 100p 68p - 100p 6.8k 16 mhz 20p - 100p 20p - 100p 6.8k 24 mhz 10p - 68p 10p - 68p 6.8k 32 mhz 5p - 20p 5p - 20p 6.8k 40 mhz 5p 5p 3.3k above table shows the reference values for crystal applications. notes: 1. c1 , c2, r components refer to figure a 2. crystal layout must get close to xtal1 and xtal2 pins on user's application board.
p reliminary w78e 858 - 26 - typical application circuits, continued expanded external d ata memory and oscillator 10 u 8.2 k dd oscillator ea 35 xtal1 21 xtal2 20 rst 10 int0 14 int1 15 t0 16 t1 17 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 p0.0 43 p0.1 42 p0.2 41 p0.3 40 p0.4 39 p0.5 38 p0.6 37 p0.7 36 p2.0 24 p2.1 25 p2.2 26 p2.3 27 p2.4 28 p2.5 29 p2.6 30 p2.7 31 rd 19 wr 18 psen 32 ale 33 txd 13 rxd 11 w78e858 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v figure b
p reliminary w 7 8e 858 publication release date: october 9, 2001 - 27 - revision a1 1 2. package dimensions 40 - pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 44 - pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q
p reliminary w78e 858 - 28 - package dimensions, continued 44 - pin pqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- q 2 q 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27516023 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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